MC68HC11KW1 Datasheet, PDF (198/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Each set of four conversions takes 144 cycles of the E-clock, provided that E is greater than or
equal to 750 kHz. If E is less than 750 kHz, an internal R-C oscillator, which is nominally 1.5 MHz,
must be used for the A/D conversion clock. When the internal R-C oscillator is being used as the
conversion clock, the conversion complete flag (CCF) must be used to determine when a
conversion sequence has been completed. When using the internal R-C oscillator for A/D
conversions, the sample and conversion process runs at the nominal 1.5 MHz rate; however, the
conversion results must be transferred to the MCU result registers synchronously with the MCU
E-clock, so conversion time is limited to a maximum of one channel per E-clock cycle.
Alternatively, if the R-C oscillator is not being used and E is greater than 2.1 MHz, the conversion
frequency can be halved to E/2 under control of the ADER bit in the ADFRQ register. Note that in
this operating mode, each set of four conversions takes 288 cycles of the E clock.
Two control bits in the OPTION register control the basic configuration of the A/D system. The A/D
power-up bit (ADPU) allows the system to be disabled, resulting in reduced power consumption when
the A/D system is not being used. Any conversion which is in process when ADPU is written to zero
will be aborted. A delay of typically 100 microseconds is required after turning on the A/D (by writing
ADPU from 0 to 1) for the analog and comparator sections to stabilize. The CSEL bit is used to select
either the internal R-C oscillator or the MCU E-clock as the A/D system clock source.
10.1
Conversion process
10
The A/D converter is ratiometric. An input voltage equal to V_RH converts to $FFC0 (full scale) and
an input voltage equal to V_RL converts to $0000. An input voltage greater than V_RH will convert to
$FFC0 with no overflow indication. Note that the six least significant bits always read zero. For
ratiometric conversions, the source of each analog input should use V_RH as the supply voltage and
be referenced to V_RL.
The A/D reference inputs are applied to a precision internal digital-to-analog converter. Control
logic drives this D/A and the analog output is successively compared to the selected analog input
which was sampled at the beginning of the conversion time. The conversion process is monotonic
with no missing codes.
10.2
Channel assignments
A multiplexer allows the single A/D converter to select one of sixteen analog signals. Ten of these
channels are supported on Port E and G input pins. Of the six other channels, two are reserved
for future use and four are for internal reference points and testing purposes. Table 10-1 shows
the signals selected by the channel select bits (CD, CC, CB, CA) in the ADCTL register. The
CONV8 bit selects either four or eight conversions. All “reserved” channels are connected to V_RL.
10-2
ANALOG-TO-DIGITAL CONVERTER
MC68HC11KW1