MC68HC11KW1 Datasheet, PDF (25/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

2.7
Nonmaskable interrupt (XIRQ)
The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization.
2
During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until
MCU software enables it. XIRQ is often used as a power loss detect interrupt.
Whenever XIRQ or IRQ is used with multiple interrupt sources (IRQ must be configured for
level-sensitive operation if there is more than one source of interrupt), each source must drive the
interrupt input with an open-drain type of driver to avoid contention between outputs. There should
be a single pull-up resistor near the MCU interrupt input pin (typically 4.7 kΩ). There must also be
an interlock mechanism at each interrupt source so that the source holds the interrupt line low until
the MCU recognizes and acknowledges the interrupt request. If one or more interrupt source is
still pending after the MCU services a request, the interrupt line will still be held low and the MCU
will be interrupted again as soon as the interrupt mask bit in the MCU is cleared (normally upon
return from an interrupt). Refer to Section 5.
2.8
MODA and MODB (MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes. Refer to Section 4.
After the operating mode has been selected, the LIR pin provides an open-drain output (driven low) to
indicate that execution of an instruction has begun. In order to detect consecutive instructions in a
high-speed application, this signal drives high for a short time to prevent false triggering. A series of E
clock cycles occurs during execution of each instruction. The LIR signal goes low during the first E
clock cycle of each instruction (opcode fetch). This output is provided for assistance in program
debugging, and its operation is controlled by the LIRDV bit in the OPT2 register.
The VSTBY pin is used to input RAM stand-by power. The MCU is powered from the VDD pin
unless the difference between the level of V_STBY and V_DD is greater than one MOS threshold
(about 0.7 volts). When these voltages differ by more than 0.7 volts, the internal RAM and part of
the reset logic are powered from V_STBY rather than V_DD. This allows RAM contents to be retained
without VDD power applied to the MCU. Reset must be driven low before V_DD is removed and must
remain low until V_DD has been restored to a valid level.
V_DD
4.8 V NiCd
(+)
V_DD V_OUT
MAX 690
V_BATT
4.7 kΩ
To MODB/VSTBY
pin of M68HC11
Figure 2-4 RAM stand-by connections
MC68HC11KW1
PIN DESCRIPTIONS
2-5