MC68HC11KW1 Datasheet, PDF (77/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.5.1 Chip select priorities
To minimize conflict between chip selects with one another or with internal memory and registers,
priority is determined by the GPSPR bit in the CSCTL register. Refer to Figure 4-12.
Table 4-12 Chip select priorities
GCSPR = 0
GCSPR = 1
4
On-chip registers
On-chip registers
On-chip RAM
On-chip RAM
Bootloader ROM
Bootloader ROM
On-chip EEPROM
On-chip EEPROM
I/O chip select
I/O chip select
Program chip select
GP chip select 1
GP chip select 1
GP chip select 2
GP chip select 2
Program chip select
4.5.2 Program chip select
The program chip select (CSPROG) is active in the range of memory where the main program
exists. Other chip selects are active when their respective memory areas are used. Refer to
Table 4-13.
CSPROG is enabled out of reset for normal expanded mode when there is no internal memory at
the reset vector address $FFFE–$FFFF. After reset in normal mode, the PCS stretch select bit in
the CSCSTR register is set to provide one cycle of stretch so that slow memory devices can be
used. In special test mode CSPROG is enabled without any stretch out of reset. Program chip
select is fixed with address valid timing and is active low.
4.5.3 I/O chip select
The I/O chip select (CSIO) is programmable for a 4K byte size located at addresses $1000 to
$1FFF, or 8K byte size located at addresses $0000 to $1FFF. Polarity of the active state is
programmable for active high or active low. Clock stretching can be set from zero to three cycles.
Refer to Section 4.5.4 for descriptions of bits IOEN, IOPL, IOCSA, and IOSZ.
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4-33