MC68HC11KW1 Datasheet, PDF (8/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

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5.1.3 COP reset ........................................................................................................5-2
5.1.3.1
COPRST — Arm/reset COP timer circuitry register...................................5-3
5.1.4 Clock monitor reset ..........................................................................................5-3
5.1.5 OPTION — System configuration options register 1 .......................................5-4
5.1.6 CONFIG — Configuration control register .......................................................5-5
5.2 Effects of reset.......................................................................................................5-6
5.2.1 Central processing unit ....................................................................................5-7
5.2.2 Memory map....................................................................................................5-7
5.2.3 Parallel I/O .......................................................................................................5-7
5.2.4 Timer 1.............................................................................................................5-7
5.2.5 Timers 2 and 3.................................................................................................5-8
5.2.6 Real-time interrupt (RTI) ..................................................................................5-8
5.2.7 Pulse accumulator ...........................................................................................5-8
5.2.8 Computer operating properly (COP)................................................................5-8
5.2.9 Serial communications interface (SCI).............................................................5-8
5.2.10 Serial peripheral interface (SPI).......................................................................5-9
5.2.11 Analog-to-digital converter...............................................................................5-9
5.2.12 System.............................................................................................................5-9
5.3 Reset and interrupt priority ....................................................................................5-9
5.3.1 HPRIO — Highest priority I-bit interrupt and misc. register .............................5-10
5.4 Interrupts ...............................................................................................................5-13
5.4.1 Interrupt recognition and register stacking.......................................................5-13
5.4.2 Nonmaskable interrupt request (XIRQ) ...........................................................5-14
5.4.3 Illegal opcode trap ...........................................................................................5-14
5.4.4 Software interrupt ............................................................................................5-14
5.4.5 Maskable interrupts .........................................................................................5-15
5.4.6 Reset and interrupt processing........................................................................5-15
5.5 Low power operation .............................................................................................5-15
5.5.1 WAIT ................................................................................................................5-15
5.5.2 STOP ...............................................................................................................5-16
6
PARALLEL INPUT/OUTPUT
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.4
6.4.1
Port A.....................................................................................................................6-2
PORTA — Port A data register ........................................................................6-2
DDRA — Data direction register for port A ......................................................6-2
Port B.....................................................................................................................6-3
PORTB — Port B data register ........................................................................6-3
DDRB — Data direction register for port B ......................................................6-3
Port C ....................................................................................................................6-4
PORTC — Port C data register........................................................................6-4
DDRC — Data direction register for port C......................................................6-4
Port D ....................................................................................................................6-5
PORTD — Port D data register........................................................................6-5
TABLE OF CONTENTS
MC68HC11KW1
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