MC68HC11KW1 Datasheet, PDF (166/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.1.3.9 TMSK2 — Timer interrupt mask register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII 0
0 PR1 PR0 0000 0000
Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer
prescaler control bits are included in this register.
Note:
Bits [7:4] in TMSK2 correspond bit for bit with the flag bits in TFLG2. Ones in bits [7:4]
of TMSK2 enable the corresponding interrupt sources.
TOI — Timer overflow interrupt enable
1 (set) – Timer overflow interrupt requested when TOF is set.
0 (clear) – TOF interrupts disabled.
RTII — Real-time interrupt enable (refer to Section 9.4)
PAOVI — Pulse accumulator overflow interrupt enable (refer to Section 9.6.3)
PAII — Pulse accumulator input edge interrupt enable (refer to Section 9.6.3)
PR[1:0] — Timer prescaler select
9
PR[1:0] Prescaler
00
1
01
4
10
8
11
16
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can only be
written once, and the write must be within 64 cycles after reset. See Table 9-1 for specific timing
values. These two bits also specify the number of divide-by-two stages that are to be inserted
between the E-clock and the timer free-running counter of Timer 3. This enables Timer 1-Timer 3
synchronization. This can, however, be overridden if a different prescale is required for Timer 3, by
writing to the Timer 3 prescale bits in the register TCTL6. See Section 9.3.5. The default state is
that the Timer 1 prescale rate is used for Timer 3.
9-14
TIMING SYSTEM
MC68HC11KW1