MC68HC11KW1 Datasheet, PDF (167/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.1.3.10 TFLG2 — Timer interrupt flag register 2
Timer interrupt flag 2 (TFLG2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0025 TOF RTIF PAOVF PAIF 0
0
0
0 0000 0000
Bits in this register indicate when certain timer system events have occurred. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a
polled or interrupt driven system. Clear flags by writing a one to the corresponding bit position(s).
Note:
Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in TMSK2 enable the
corresponding interrupt sources.
TOF — Timer overflow interrupt flag
1 (set) – TCNT has overflowed from $FFFF to $0000.
0 (clear) – No timer overflow has occurred.
RTIF — Real time (periodic) interrupt flag (refer to Section 9.4)
PAOVF — Pulse accumulator overflow interrupt flag (refer to Section 9.6)
PAIF — Pulse accumulator input edge interrupt flag (refer to Section 9.6.)
Bits [3:0] — Not implemented; always read zero
9
9.2
Timer 2
Timer 2 comprises a 4-stage prescaler and a 16-bit counter. It has three associated 16-bit output
compare registers along with a software-programmable input capture or output compare register.
The functions of Timer 2 share I/O with the pins of port J as follows:
Pin Alternative function
PJ3 ECIN
PJ4 OC1
PJ5 OC2
PJ6 OC3
PJ7 C4
The Timer 2 prescaler is a 4 stage divider with the E clock as its input. Prescaling factors of 1, 4,
8 or 16 can be selected by the P2RA and P2RB bits in the TCTL4 register. Timer 2 also offers an
MC68HC11KW1
TIMING SYSTEM
9-15