MC68HC11KW1 Datasheet, PDF (62/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Mode
Single chip
Expanded
Boot
Special test
IRVNE
after reset
0
0
0
1
E clock
IRV
IRVNE
IRVNE
after reset after reset affects only can be written
On
Off
E
Once
On
Off
IRV
Once
On
Off
E
Unlimited
On
On
IRV
Unlimited
LSBF — LSB-first enable (refer to Section 8)
4
1 (set) – Data is transferred LSB first.
0 (clear) – Data is transferred MSB first.
SPR2 — SPI clock rate select (refer to Section 8)
This bit adds a divide-by-four to the SPI clock chain.
XDV[1, 0] — XOUT clock divide select
These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if
enabled by the CLKX bit in CONFIG. Table 4-7 shows some example frequencies. Once a clock
rate has been selected, a maximum time of 16 E clock cycles should be allowed for the signal to
stabilize. Note that on reset, both bits are cleared and the XCLK signal runs at the same frequency
as EXTAL.
Note: The phase relationship between XOUT and EXTAL or E cannot be predicted.
Table 4-7 XCLK frequencies
XDV
1
XDV2
00
01
10
11
EXTAL divided by
1
4
6
8
XCLK with EXTAL = 16 MHz
16 MHz
4 MHz
2.7 MHz
2 MHz
4.3.2.6 BPROT — Block protect register
Block protect (BPROT)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0035 BULKP BIT6 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1111 1111
BPROT prevents accidental writes to EEPROM and the CONFIG register, and enables the low
voltage EEPROM protect circuit. The bits in this register can be written to zero only once during
4-18
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1