MC68HC11KW1 Datasheet, PDF (56/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.3.2 Initialization
Because bits in the following registers control the basic configuration of the MCU, an accidental
change of their values could cause serious system problems. The protection mechanism,
overridden in special operating modes, requires a write to the protected bits only within the first 64
bus cycles after any reset, or only once after each reset. See Table 4-3.
4 ^{4.3.2.1 CONFIG — System configuration register}
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Configuration control (CONFIG) $003F 1
1
CLKX
PAREN
NOSEC
NOCO
P
1
EEON 11xx xx1x
CONFIG controls the presence of EEPROM in the memory map and enables the COP watchdog
system. The CLKX bit enables the XOUT pin to output the XCLK signal, and the PAREN bit
enables pull-ups on certain ports. Refer to Section 4.6.3. A security feature that protects data in
EEPROM and RAM is available, controlled by the NOSEC bit (refer to Section 4.6.3).
CONFIG is made up of EEPROM cells and static working latches. The operation of the MCU is
controlled directly by these latches and not the EEPROM byte. When programming the CONFIG
register, the EEPROM byte is accessed. When the CONFIG register is read, the static latches are
accessed.
These bits can be read at any time. The value read is the one latched into the register from the
EEPROM cells during the last reset sequence. A new value programmed into this register is not
readable until after a subsequent reset sequence.
Bits in CONFIG can be written at any time if SMOD = 1 (bootstrap or special test mode). If
SMOD = 0 (single chip or expanded mode), these bits can only be written using the EEPROM
programming sequence, and none of the bits are readable or active until latched via the next reset.
Bits [7, 6, 1] — Not implemented; always read as one.
CLKX — XOUT enable
1 (set) – XCLK signal is driven out on the XOUT pin.
0 (clear) – XOUT pin is disabled.
The frequency of the XCLK signal is controlled by two bits in the OPT2 register (see
Section 4.3.2.5).
PAREN — Pull-up assignment register enable (refer to Section 6)
1 (set) – Pull-ups can be enabled using PPAR.
0 (clear) – All pull-ups disabled (not controlled by PPAR).
4-12
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1