SH7101 Datasheet, PDF (94/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Processing
5.3.2 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends, the current
instruction finishes, and then address error exception processing starts. The CPU operates as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the occurred address error, and the program starts executing
from that address. The jump in this case is not a delayed branch.
5.4 Interrupts
5.4.1 Interrupt Sources
Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, IRQ and
on-chip peripheral modules.
Table 5.7 Interrupt Sources
Type
NMI
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
IRQ0 to IRQ3 pins (external input)
Multifunction timer unit
Compare match timer
A/D converter (A/D0 and A/D1)
Serial communication interface
Watchdog timer
Input/output port
Number of Sources
1
4
23
2
2
8
1
1
Each interrupt source is allocated a different vector number and vector table offset. See section 6,
Interrupt Controller (INTC), and table 6.2, Interrupt Exception Processing Vectors and Priorities,
for more information on vector numbers and vector table address offsets.
Rev.2.00 Sep. 27, 2007 Page 60 of 448
REJ09B0394-0200