SH7101 Datasheet, PDF (356/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
10.7 Interrupts Sources
10.7.1 Interrupts in Normal Serial Communication Interface Mode
Table 10.10 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 10.10 SCI Interrupt Sources
Channel
2
3
Name
ERI_2
RXI_2
TXI_2
TEI_2
ERI_3
RXI_3
TXI_3
TEI_3
Interrupt Source
Receive Error
Receive Data Full
Transmit Data Empty
Transmission End
Receive Error
Receive Data Full
Transmit Data Empty
Transmission End
Interrupt Flag
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
Rev.2.00 Sep. 27, 2007 Page 322 of 448
REJ09B0394-0200