SH7101 Datasheet, PDF (55/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Addressing
Mode
Indirect register
addressing with
displacement
Instruction
Format
Effective Address Calculation
Equation
@(disp:4, The effective address is the sum of Rn and a 4-bit
Rn)
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
1/2/4
Indirect indexed @(R0, Rn) The effective address is the sum of Rn and R0.
register
addressing
Rn
+
Rn + R0
Rn + R0
R0
Indirect GBR
addressing with
displacement
@(disp:8, The effective address is the sum of GBR value and Byte:
GBR)
an 8-bit displacement (disp). The value of disp is GBR + disp
zero-extended, and remains unchanged for a byte _Word:
operation, is doubled for a word operation, and is _{GBR + disp ×}
quadrupled for a longword operation.
2
GBR
disp
(zero-extended)
Longword:
GBR + disp ×
+
GBR
+ disp × 1/2/4
4
×
Indirect indexed @(R0,
GBR addressing GBR)
1/2/4
The effective address is the sum of GBR value and GBR + R0
R0.
GBR
+
GBR + R0
R0
Rev.2.00 Sep. 27, 2007 Page 21 of 448
REJ09B0394-0200