SH7101 Datasheet, PDF (307/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Watchdog Timer
9.5 Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 9.2 WDT Interrupt Source (in Interval Timer Mode)
Name
ITI
Interrupt Source
TCNT overflow
Interrupt Flag
OVF
9.6 Usage Notes
9.6.1 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
TCNT and TCSR both have the same write address. The write data must be contained in the lower
byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure
9.6). This transfers the write data from the lower byte to TCNT or TCSR.
• Writing to TCNT
15
Address: H'FFFF8610
H'5A
87
0
Write data
• Writing to TCSR
15
Address: H'FFFF8610
H'A5
87
0
Write data
Figure 9.6 Writing to TCNT and TCSR
Rev.2.00 Sep. 27, 2007 Page 273 of 448
REJ09B0394-0200