SH7101 Datasheet, PDF (102/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
6.2 Input/Output Pins
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Non-maskable interrupt input pin
Interrupt request input pins
Interrupt request output pin
Abbreviation I/O
NMI
I
IRQ0 to IRQ3 I
IRQOUT
O
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
Output of notification signal when an
interrupt has occurred
6.3 Register Descriptions
The interrupt controller has the following registers. For details on register addresses and register
states during each processing, refer to section 18, List of Registers.
• Interrupt control register 1 (ICR1)
• Interrupt control register 2 (ICR2)
• IRQ status register (ISR)
• Interrupt priority register A (IPRA)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
Rev.2.00 Sep. 27, 2007 Page 68 of 448
REJ09B0394-0200