SH7101 Datasheet, PDF (7/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Main Revisions for This Edition
Item
All
Page
⎯
6.5 Interrupt Exception 79
Processing Vectors
Table
Table 6.2 Interrupt
Exception Processing
Vectors and Priorities
7.5.1 Bus Control
89
Register 1 (BCR1)
8.1 Features
94
Figure 8.1 Block
Diagram of MTU
8.3.3 Timer I/O Control 109
Register (TIOR)
Table 8.13 TIORL_0
(channel 0)
8.4.4 Cascaded
149
Operation
Table 8.30 Cascaded
Combinations
Revision (See Manual for Details)
• Company name and brand names amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
Table amended
Interrupt
Source
Name
MTU channel 3 TGIA_3
TGIB_3
TGIC_3
TGID_3
TCIV_3
Bit table amended
Initial
Bit Bit Name Value R/W
14
⎯
1
R
Title and figure amended
Description
Reserved
These bits are always read as 1 and should always be
written to 1.
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TGI4C
TGI4D
TCI4V
Table amended
Bit 3
IOC3
0
Bit 2
IOC2
0
Bit 1
IOC1
0
Bit 0
IOC0
0
1
TGRC_0
Function
Output
compare
register*
Description
TIOC0C Pin Function
Output disable
Initial output is 0
0 output at compare match
Note amended
Note: When phase counting mode is set for channel 1 or 2, the
counter clock setting is invalid and the counters operates
independently in phase counting mode.
Rev.2.00 Sep. 27, 2007 Page vii of xxxiv
REJ09B0394-0200