SH7101 Datasheet, PDF (157/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Initial
Bit Bit Name value R/W
2
TGIEC
0
R/W
1
TGIEB
0
R/W
0
TGIEA
0
R/W
8. Multi-Function Timer Pulse Unit (MTU)
Description
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 2 is reserved. It is always read as
0, and the write value should always be 0.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev.2.00 Sep. 27, 2007 Page 123 of 448
REJ09B0394-0200