SH7101 Datasheet, PDF (294/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Output-Level Compare Operation
Figure 8.115 shows an example of the output-level compare operation for the combination of
PE9/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations.
Pφ
PE9/
TIOC3B
PE11/
TIOC3D
0 level overlapping detected
High impedance state
Figure 8.115 Output-Level Detection Operation
Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-current pins that have become high-
impedance due to output-level detection can be released either by returning them to their initial
state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level
compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance
state by clearing the OSF flag, always do so only after outputting a high level from the high-
current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs
can be achieved by setting the MTU internal registers.
Rev.2.00 Sep. 27, 2007 Page 260 of 448
REJ09B0394-0200