SH7101 Datasheet, PDF (48/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Initial
Bit
Bit Name Value
R/W Description
0
T
Undefined R/W
T bit
The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF
(BF/S), SETT, and CLRT instructions use the T bit to
indicate true (1) or false (0).
The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S,
DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR, and ROTCL instructions also use the
T bit to indicate carry/borrow or overflow/underflow.
Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode.
The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register
areas and in logic operations.
Vector Base Register (VBR): Indicates the base address of the exception processing vector area.
2.2.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC).
Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-and-
accumulate operations.
Procedure Register (PR): Registers to store the return address from a subroutine procedure.
Program Counter (PC): Registers to indicate the sum of current instruction addresses and four,
that is, the address of the second instruction after the current instruction.
Rev.2.00 Sep. 27, 2007 Page 14 of 448
REJ09B0394-0200