SH7101 Datasheet, PDF (299/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Watchdog Timer
9.3 Register Descriptions
The WDT has the following three registers. For details, refer to section 18, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method
different from normal registers. For details, refer to section 9.6.1, Notes on Register Access.
• Timer control/status register (TCSR)
• Timer counter (TCNT)
• Reset control/status register (RSTCSR)
9.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected
by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows
(changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer
interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR.
Rev.2.00 Sep. 27, 2007 Page 265 of 448
REJ09B0394-0200