SH7101 Datasheet, PDF (238/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
8.7 Usage Notes
8.7.1 Module Standby Mode Setting
MTU operation can be disabled or enabled using the module standby register. The initial setting is
for MTU operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 17, Power-Down Modes.
8.7.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.69 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap ence Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev.2.00 Sep. 27, 2007 Page 204 of 448
REJ09B0394-0200