SH7101 Datasheet, PDF (66/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Instruction
Instruction Code
MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
MOV.B R0,@(disp,GBR) 11000000dddddddd
MOV.W R0,@(disp,GBR) 11000001dddddddd
MOV.L R0,@(disp,GBR) 11000010dddddddd
MOV.B @(disp,GBR),R0 11000100dddddddd
MOV.W @(disp,GBR),R0 11000101dddddddd
MOV.L @(disp,GBR),R0 11000110dddddddd
MOVA @(disp,PC),R0 11000111dddddddd
MOVT Rn
0000nnnn00101001
SWAP.B Rm,Rn
0110nnnnmmmm1000
SWAP.W Rm,Rn
0110nnnnmmmm1001
XTRCT Rm,Rn
0010nnnnmmmm1101
Operation
(disp × 4 + Rm) → Rn
Rm → (R0 + Rn)
Rm → (R0 + Rn)
Rm → (R0 + Rn)
(R0 + Rm) → Sign
extension → Rn
(R0 + Rm) → Sign
extension → Rn
(R0 + Rm) → Rn
R0 → (disp + GBR)
R0 → (disp × 2 + GBR)
R0 → (disp × 4 + GBR)
(disp + GBR) → Sign
extension → R0
(disp × 2 + GBR) → Sign
extension → R0
(disp × 4 + GBR) → R0
disp × 4 + PC → R0
T → Rn
Rm → Swap bottom two
bytes → Rn
Rm → Swap two
consecutive words → Rn
Rm: Middle 32 bits of
Rn → Rn
Execu-
tion
T
States Bit
1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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Rev.2.00 Sep. 27, 2007 Page 32 of 448
REJ09B0394-0200