SH7101 Datasheet, PDF (14/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4.1.1 Connecting Crystal Resonator ................................................................................ 47
4.1.2 External Clock Input Method.................................................................................. 49
4.2 Function for Detecting Oscillator Halt................................................................................. 49
4.3 Usage Notes ......................................................................................................................... 50
4.3.1 Note on Crystal Resonator ...................................................................................... 50
4.3.2 Notes on Board Design ........................................................................................... 50
Section 5 Exception Processing...........................................................................53
5.1 Overview.............................................................................................................................. 53
5.1.1 Types of Exception Processing and Priority ........................................................... 53
5.1.2 Exception Processing Operations............................................................................ 54
5.1.3 Exception Processing Vector Table ........................................................................ 55
5.2 Resets ................................................................................................................................ 57
5.2.1 Types of Reset ........................................................................................................ 57
5.2.2 Power-On Reset ...................................................................................................... 57
5.2.3 Manual Reset .......................................................................................................... 58
5.3 Address Errors ..................................................................................................................... 59
5.3.1 Cause of Address Error Exception.......................................................................... 59
5.3.2 Address Error Exception Processing....................................................................... 60
5.4 Interrupts.............................................................................................................................. 60
5.4.1 Interrupt Sources..................................................................................................... 60
5.4.2 Interrupt Priority Level ........................................................................................... 61
5.4.3 Interrupt Exception Processing ............................................................................... 61
5.5 Exceptions Triggered by Instructions .................................................................................. 62
5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 62
5.5.2 Trap Instructions ..................................................................................................... 62
5.5.3 Illegal Slot Instructions ........................................................................................... 63
5.5.4 General Illegal Instructions..................................................................................... 63
5.6 Cases when Exception Sources are Not Accepted ............................................................... 64
5.6.1 Immediately after Delayed Branch Instruction ....................................................... 64
5.6.2 Immediately after Interrupt-Disabled Instruction ................................................... 64
5.7 Stack Status after Exception Processing Ends ..................................................................... 65
5.8 Usage Notes ......................................................................................................................... 66
5.8.1 Value of Stack Pointer (SP) .................................................................................... 66
5.8.2 Value of Vector Base Register (VBR) .................................................................... 66
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing......... 66
Section 6 Interrupt Controller (INTC).................................................................67
6.1 Features................................................................................................................................ 67
6.2 Input/Output Pins ................................................................................................................. 68
Rev.2.00 Sep. 27, 2007 Page xiv of xxxiv
REJ09B0394-0200