SH7101 Datasheet, PDF (334/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
10.4.4 SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below. When the operating mode, transfer format, etc., is changed,
the TE and RE bits must be cleared to 0 before making the change using the following procedure.
When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does
not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When the external clock is used in asynchronous mode, the clock must be supplied even during
initialization.
Start transmission
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCR to 0*
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SMR
[2]
Set value in BRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set the RIE, TIE, TEIE,
[4]
and MPIE bits in SCR
Set PFC of the external pin used _[5]
SCK, TxD, RxD
Set TE and RE bits of SCR to 1 _[6]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if an
external colck is used.
[4] Set the RIE, TIE, TEIE, and MPIE
bits.
[5] Set PFC of the external pin used.
Set RxD input during receiving and
TxD output during transmitting. Set
SCK input/output according to
contents set by CKE1 and CKE0.
When CKE1 and CKE0 are 0 in
asynchronous mode, setting the
SCK pin is unnecessary.
Outputting clocks from the SCK pin
starts at synchronous clock output
setting.
[6] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to
1.* At this time, the TxD, RxD, and
SCK pins can be used. The TxD
pin is in a mark state during
transmitting, and RxD pin is in an
idle state for waiting the start bit
during receiving.
< Initialization completion>
Note: * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1
simultaneously.
Figure 10.5 Sample SCI Initialization Flowchart
Rev.2.00 Sep. 27, 2007 Page 300 of 448
REJ09B0394-0200