SH7101 Datasheet, PDF (226/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Complementary PWM Mode Output Protection Function
Complementary PWM mode output has the following protection functions.
• Register and counter miswrite prevention function
With the exception of the buffer registers, which can be rewritten at any time, access by the
CPU can be enabled or disabled for the mode registers, control registers, compare registers,
and counters used in complementary PWM mode by means of bit 13 in the bus controller's bus
control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total
21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4;
TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and
TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function
enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to
the mode registers, control registers, and counters. In access disabled state, an undefined value
is read from the registers concerned, and cannot be modified.
• Halting of PWM output by external signal
The 6-phase PWM output pins can be set automatically to the high-impedance state by
inputting specified external signals. There are four external signal input pins.
See section 8.9, Port Output Enable (POE), for details.
• Halting of PWM output when oscillator is stopped
If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins
automatically go to the high-impedance state. The pin states are not guaranteed when the clock
is restarted.
For details, see section 4.2, Function for Detecting Oscillator Halt.
8.5 Interrupt Sources
8.5.1 Interrupts and Priorities
There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 6, Interrupt Controller (INTC).
Rev.2.00 Sep. 27, 2007 Page 192 of 448
REJ09B0394-0200