SH7101 Datasheet, PDF (104/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
Initial
Bit Bit Name Value
4
IRQ3S
0
3 to 0 ⎯
All 0
R/W Description
R/W IRQ3 Sense Select
This bit sets the IRQ3 interrupt request detection mode.
0: Interrupt request is detected on low level of IRQ3 input
1: Interrupt request is detected on edge of IRQ3 input
(edge direction is selected by ICR2)
R
Reserved
These bits are always read as 0. The write value should
always be 0.
6.3.2 Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0
to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the
edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1
(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the
setting of ICR2 is ignored.
Initial
Bit Bit Name Value R/W Description
15
IRQ0ES1 0
14
IRQ0ES0 0
R/W This bit sets the IRQ0 interrupt request edge detection
R/W ^mode.
00: Interrupt request is detected on falling edge of IRQ0
input
01: Interrupt request is detected on rising edge of IRQ0
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ0 input
11: Cannot be set
Rev.2.00 Sep. 27, 2007 Page 70 of 448
REJ09B0394-0200