SH7101 Datasheet, PDF (381/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Compare Match Timer (CMT)
12.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral
clock (Pφ) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.
Pφ
Internal
clock
CMCNT
input clock
CMCNT
N-1
N
N+1
Figure 12.3 Count Timing
12.4 Interrupts
12.4.1 Interrupt Sources
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when interrupt request
flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for
details.
12.4.2 Compare Match Flag Set Timing
The CMF bit in CMCSR is set to 1 by the compare match signal generated when the CMCOR
register and the CMCNT counter match. The compare match signal is generated upon the final
state of the match (timing at which the CMCNT counter matching count value is updated).
Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal
will not be generated until a CMCNT counter input clock occurs. Figure 12.4 shows the CMF bit
set timing.
Rev.2.00 Sep. 27, 2007 Page 347 of 448
REJ09B0394-0200