SH7101 Datasheet, PDF (25/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)... 190
Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)... 191
Count Timing in Internal Clock Operation............................................................. 195
Count Timing in External Clock Operation ........................................................... 195
Count Timing in External Clock Operation (Phase Counting Mode)..................... 196
Output Compare Output Timing (Normal Mode/PWM Mode).............................. 196
Output Compare Output Timing
(Complementary PWM Mode/Reset Synchronous PWM Mode) .......................... 197
Input Capture Input Signal Timing......................................................................... 197
Counter Clear Timing (Compare Match) ............................................................... 198
Counter Clear Timing (Input Capture) ................................................................... 198
Buffer Operation Timing (Compare Match) .......................................................... 199
Buffer Operation Timing (Input Capture) .............................................................. 199
TGI Interrupt Timing (Compare Match) ................................................................ 200
TGI Interrupt Timing (Input Capture) .................................................................... 201
TCIV Interrupt Setting Timing............................................................................... 202
TCIU Interrupt Setting Timing............................................................................... 202
Timing for Status Flag Clearing by the CPU ......................................................... 203
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. 204
Contention between TCNT Write and Clear Operations........................................ 205
Contention between TCNT Write and Increment Operations ................................ 206
Contention between TGR Write and Compare Match ........................................... 207
Contention between Buffer Register Write and Compare Match (Channel 0) ....... 208
Contention between Buffer Register Write and Compare Match
(Channels 3 and 4).................................................................................................. 209
Contention between TGR Read and Input Capture ................................................ 210
Contention between TGR Write and Input Capture ............................................... 211
Contention between Buffer Register Write and Input Capture............................... 212
TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection.. 213
Counter Value during Complementary PWM Mode Stop ..................................... 214
Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode.............. 215
Reset Sync PWM Mode Overflow Flag ................................................................. 216
Contention between Overflow and Counter Clearing ............................................ 217
Contention between TCNT Write and Overflow.................................................... 218
Error Occurrence in Normal Mode, Recovery in Normal Mode............................ 223
Error Occurrence in Normal Mode, Recovery in PWM Mode 1............................ 224
Error Occurrence in Normal Mode, Recovery in PWM Mode 2............................ 225
Error Occurrence in Normal Mode, Recovery in Phase Counting Mode ............... 226
Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode .... 227
Rev.2.00 Sep. 27, 2007 Page xxv of xxxiv
REJ09B0394-0200