SH7101 Datasheet, PDF (321/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
10.3.8 Serial Direction Control Register (SDCR)
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer.
With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode. With a 7-bit data length, LSB-first transfer must be selected. The
description in this section assumes LSB-first transfer.
Initial
Bit Bit Name Value R/W
7 to 4 ⎯
All 1
R
3
DIR
0
R/W
2
⎯
1
⎯
0
⎯
0
R
1
R
0
R
Description
Reserved
The write value must always be 1. Operation cannot be
guaranteed if 0 is written.
Data Transfer Direction
Selects the serial/parallel conversion format. Valid for an
8-bit transmit/receive format.
0: TDR contents are transmitted in LSB-first order
Receive data is stored in RDR in LSB-first
1: TDR contents are transmitted in MSB-first order
Receive data is stored in RDR in MSB-first
Reserved
The write value must always be 0. Operation cannot be
guaranteed if 1 is written.
Reserved
This bit is always read as 1, and cannot be modified.
Reserved
The write value must always be 0. Operation cannot be
guaranteed if 1 is written.
10.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 10.2 shows
the relationships between the N setting in BRR and the effective bit rate B₀ for asynchronous and
clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by
the CPU at all times.
Rev.2.00 Sep. 27, 2007 Page 287 of 448
REJ09B0394-0200