SH7101 Datasheet, PDF (58/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.4.3 Instruction Format
The instruction formats and the meaning of source and destination operand are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx xxxx
0
xxxx
Source
Operand
⎯
Destination
Operand
⎯
Example
NOP
n format
15
xxxx nnnn
0
xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
⎯
Control register or
system register
Control register or
system register
mmmm: Direct
register
mmmm: Indirect
post-increment
register
mmmm: Indirect
register
mmmm: PC
relative using Rm
nnnn: Direct
register
MOVT Rn
nnnn: Direct
register
STS MACH,Rn
nnnn: Indirect pre- STC.L SR,@-Rn
decrement register
Control register or LDC
system register
Rm,SR
Control register or LDC.L @Rm+,SR
system register
⎯
JMP @Rm
⎯
BRAF Rm
Rev.2.00 Sep. 27, 2007 Page 24 of 448
REJ09B0394-0200