SH7101 Datasheet, PDF (67/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Arithmetic Operation Instructions
Table 2.13 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
0100nnnn00010001
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Execu-
tion
States
1
1
1
1
1
If Rn = Rm, 1 → T
1
If Rn ≥ Rm with unsigned 1
data, 1 → T
If Rn ≥ Rm with signed 1
data, 1 → T
If Rn > Rm with unsigned 1
data, 1 → T
If Rn > Rm with signed 1
data, 1 → T
If Rn > 0, 1 → T
1
If Rn ≥ 0, 1 → T
1
If Rn and Rm have
1
an equivalent byte,
1→T
Single-step division (Rn 1
÷ Rm)
MSB of Rn → Q, MSB 1
of Rm → M, M ^ Q → T
T Bit
⎯
⎯
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
Rev.2.00 Sep. 27, 2007 Page 33 of 448
REJ09B0394-0200