SH7101 Datasheet, PDF (364/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. A/D Converter
Table 11.2 Channel Select List
Analog Input Channels
Bit 2 Bit 1 Bit 0
Single Mode
4-Channel Scan Mode*
CH2 CH1 CH0 A/D0
A/D1
A/D0
A/D1
1
0
0
AN8
AN12
AN8
AN12
1
AN9
AN13
AN8, AN9
AN12, AN13
1
0
AN10
AN14
AN8 to AN10 AN12 to AN14
1
AN11
AN15
AN8 to AN11 AN12 to AN15
Note: * Continuous scan mode or single-cycle scan mode can be selected with the ADCS bit.
11.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1)
ADCR for each module controls A/D conversion started by an external trigger signal and selects
the operating clock.
Initial
Bit Bit Name Value R/W
7
TRGE
0
R/W
6
CKS1
0
R/W
5
CKS0
0
R/W
Description
Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG or an MTU trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
Clock Select 0 and 1
Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the A/D conversion time, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
CKS [1,0] = b'11 can be set while Pφ ≤ 25 MHz.
Rev.2.00 Sep. 27, 2007 Page 330 of 448
REJ09B0394-0200