SH7101 Datasheet, PDF (370/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. A/D Converter
A/D conversion time (t_CONV)
A/D conversion start Analog input
delay time(t_D) sampling time(t_SPL)
Write cycle
A/D synchronization time
(Up to
(3 states) _{59 states)}
Pφ
Address
Internal write
signal
Analog input
sampling
signal
A/D converter
ADST write timing
Idle state
Sample-and-hold A/D conversion
ADF
End of A/D conversion
Figure 11.3 A/D Conversion Timing
Table 11.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS0 = 0
CKS0 = 1
Item
Symbol Min Typ Max Min Typ Max
A/D conversion t_D
start delay time
31 ⎯ 62 15 ⎯ 30
Input sampling t_SPL
time
⎯ 256 ⎯ ⎯ 128 ⎯
A/D conversion t_CONV
time
1024 ⎯ 1055 515 ⎯ 530
Note: All values represent the number of states for Pφ.
CKS1 = 1
CKS0 = 0
CKS0 = 1
Min Typ Max Min Typ Max
7 ⎯ 14 3 ⎯ 6
⎯ 64 ⎯ ⎯ 32 ⎯
259 ⎯ 266 131 ⎯ 134
Rev.2.00 Sep. 27, 2007 Page 336 of 448
REJ09B0394-0200