SH7101 Datasheet, PDF (119/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
Interrupt acceptance
1
3
5 + m1 + m2 + m3
3
m1 m2 1 m3 1
IRQ
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
F DE E MMEME E
F
FDE
Legend:
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed according to the results
of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted
Rev.2.00 Sep. 27, 2007 Page 85 of 448
REJ09B0394-0200