SH7101 Datasheet, PDF (417/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Mask ROM
15. Mask ROM
This LSI is available with 32 kbytes of on-chip mask ROM. The on-chip ROM is connected to the
CPU through a 32-bit data bus (figure 15.1). The CPU can access the on-chip ROM in 8, 16 and
32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'00007FFC
H'00007FFD
H'00007FFE
H'00007FFF
Figure 15.1 Mask ROM Block Diagram
The on-chip ROM is allocated to addresses H'00000000 to H'00007FFF.
15.1 Usage Note
• Setting module standby mode
For mask ROM, this module can be disabled/enabled by the module standby control register.
Mask ROM operation is enabled for the initial value. Accessing mask ROM is disabled by
setting module standby mode. For details, see section 17, Power-Down Modes.
Rev.2.00 Sep. 27, 2007 Page 383 of 448
REJ09B0394-0200