SH7101 Datasheet, PDF (40/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
Type
Symbol
Operating FWP
mode control
I/O
Input
System
control
RES
MRES
WDTOVF
Input
Input
Output
Interrupts
NMI
Input
IRQ3 to IRQ0 Input
IRQOUT
Multi function TCLKA
timer-pulse TCLKB
unit (MTU) TCLKC
TCLKD
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
Output
Input
Input/
Output
Input/
Output
TIOC2A
TIOC2B
Input/
Output
Name
Function
Protection
Pin for the flash memory. This pin is only
against write used in the flash memory version. Writing
operation into or erasing of flash memory can be
Flash memory protected. This pin becomes the Vcc pin
for the mask ROM version.
Power on
reset
When this pin is driven low, the chip
becomes to power on reset state.
Manual reset When this pin is driven low, the chip
becomes to manual reset state.
Watchdog
Output signal for the watchdog timer
timer overflow overflow. This pin should be pulled down
with at least 1 MΩ resistor value.
Non-maskable Non-maskable interrupt pin. If this pin is
interrupt
not used, it should be fixed high or low.
Interrupt
request 3 to 0
These pins request a maskable interrupt.
One of the level input or edge input can be
selected. In case of the edge input, one of
the rising edge, falling edge, or both can
be selected.
Interrupt
Shows that an interrupt cause has
request output occurred.
External clock These pins input an external clock.
input for MTU
timer
MTU input
The TGRA_0 to TGRD_0 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 0)
MTU input
The TGRA_1 to TGRB_1 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 1)
MTU input
The TGRA_2 to TGRB_2 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 2)
Rev.2.00 Sep. 27, 2007 Page 6 of 448
REJ09B0394-0200