SH7101 Datasheet, PDF (244/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
8.7.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 8.75 shows the timing in this case.
TGR read cycle
T1
T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal data bus
M
Figure 8.75 Contention between TGR Read and Input Capture
Rev.2.00 Sep. 27, 2007 Page 210 of 448
REJ09B0394-0200