SH7101 Datasheet, PDF (317/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
10.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 10.7, Interrupts Sources.
Initial
Bit Bit Name Value R/W
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is prohibited.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 10.5,
Multiprocessor Communication Function.
Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
Rev.2.00 Sep. 27, 2007 Page 283 of 448
REJ09B0394-0200