SH7101 Datasheet, PDF (382/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Compare Match Timer (CMT)
Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 12.4 CMF Set Timing
12.4.3 Compare Match Flag Clear Timing
The CMF bit in CMCSR is cleared by writing 0 to it after reading 1. Figure 12.5 shows the timing
when the CMF bit is cleared by the CPU.
CMCSR write cycle
T1 T2
Pφ
CMF
Figure 12.5 Timing of CMF Clear by CPU
Rev.2.00 Sep. 27, 2007 Page 348 of 448
REJ09B0394-0200