SH7101 Datasheet, PDF (252/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
8.7.17 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 8.83 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 8.83 Contention between TCNT Write and Overflow
8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-
Synchronous PWM Mode
When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset-
synchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D,
TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to
reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct.
When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to
registers TIOR3_H, TIOR3_L, TIOR4_H, and TIOR4_L to initialize the output pins to low level
output, then set an initial register value of H'00 before making the mode transition.
When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to
normal operation, then initialize the output pins to low level output and set an initial register value
of H'00 before making the transition to reset-synchronous PWM mode.
Rev.2.00 Sep. 27, 2007 Page 218 of 448
REJ09B0394-0200