SH7101 Datasheet, PDF (57/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Addressing
Mode
PC relative
addressing
Immediate
addressing
2. CPU
Instruction
Format
Effective Address Calculation
Equation
Rn
The effective address is the sum of the register PC PC + Rn
and Rn.
PC
+
PC + Rn
#imm:8
#imm:8
#imm:8
Rn
The 8-bit immediate data (imm) for the TST, AND, ⎯
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, ⎯
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA ⎯
instruction is zero-extended and then quadrupled.
Rev.2.00 Sep. 27, 2007 Page 23 of 448
REJ09B0394-0200