SH7101 Datasheet, PDF (106/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
6.3.3 IRQ Status Register (ISR)
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing 0 to IRQnF after reading IRQnF = 1.
Initial
Bit
Bit Name Value R/W Description
15 to 8 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
IRQ0F
0
R/W IRQ0 to IRQ3 Flags
6
IRQ1F
0
5
IRQ2F
0
4
IRQ3F
0
R/W These bits display the IRQ0 to IRQ3 interrupt request
R/W
status.
R/W
[Setting condition]
• When interrupt source that is selected by ICR1 and
ICR2 has occurred.
3 to 0 ⎯
All 0
R
[Clearing conditions]
• When 0 is written after reading IRQnF = 1
• When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
• When IRQn interrupt exception processing has
been executed under the edge detection mode of
falling edge, rising edge or both of falling and rising
edge.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.2.00 Sep. 27, 2007 Page 72 of 448
REJ09B0394-0200