SH7101 Datasheet, PDF (383/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Compare Match Timer (CMT)
12.5 Usage Notes
12.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
12.6 shows the timing.
CMCNT write cycle
T1 T2
Pφ
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H'0000
Figure 12.6 CMCNT Write and Compare Match Contention
Rev.2.00 Sep. 27, 2007 Page 349 of 448
REJ09B0394-0200