SH7101 Datasheet, PDF (182/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
• When TGR is an input capture register
Figure 8.17 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the
occurrence of input capture A, the value previously stored in TGRA is simultaneously
transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
Time
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 8.17 Example of Buffer Operation (2)
Rev.2.00 Sep. 27, 2007 Page 148 of 448
REJ09B0394-0200