SH7101 Datasheet, PDF (287/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
The POE has input-level detection circuitry and output-level detection circuitry, as shown in the
block diagram of figure 8.113.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Output level
detection circuit
Output level
detection circuit
Output level
detection circuit
OCSR
ICSR1
POE3
POE2
POE1
POE0
Input level detection circuit
Falling-edge
detection circuit
Low-level
detection circuit
High-
impedance
request control
signal
Interrupt request
(MTUPOE)
Pφ/8
Pφ/16
Pφ/128
Legend:
OCSR: Output level control/status register
ICSR1: Input level control/status register
Figure 8.113 POE Block Diagram
Rev.2.00 Sep. 27, 2007 Page 253 of 448
REJ09B0394-0200