SH7101 Datasheet, PDF (309/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Watchdog Timer
9.6.2 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented. Figure 9.8 shows this operation.
TCNT write cycle
T1
T2
T3
φ
Address
TCNT address
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 9.8 Contention between TCNT Write and Increment
9.6.3 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while
the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by
clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0.
9.6.4 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
Rev.2.00 Sep. 27, 2007 Page 275 of 448
REJ09B0394-0200