SH7101 Datasheet, PDF (462/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Electrical Characteristics
19.3.3 Control Signal Timing
Table 19.5 shows control signal timing.
Table 19.5 Control Signal Timing
Conditions: V_CC = 4.0 V to 5.5 V, AV_CC = 4.0 V to 5.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C
to +75°C (Standard product)*¹, T_a = –40°C to +85°C (Wide temperature-range
product)* ¹
Item
Symbol Min Max Unit Figures
RES rise time, fall time
t , t _{RESr RESf}
⎯
RES pulse width
t_RESW
25
RES setup time
t
19
RESS
MRES pulse width
t_MRESW
20
MRES setup time
t_MRESS
19
MD3 to MD0, FWP setup time
t_MDS
20
NMI rise time, fall time
t , t _{NMIr NMIIf}
⎯
NMI setup time
t_NMIS
19
IRQ3 to IRQ0 setup time*² (edge detection) t_IRQES
19
IRQ3 to IRQ0 setup time*² (level detection) t_IRQLS
19
NMI hold time
t_NMIH
19
IRQ3 to IRQ0 hold time
t_IRQEH
19
IRQOUT output delay time
t_IRQOD
⎯
[Operating precautions]
200
ns
Figure 19.5
⎯
t_cyc
Figure 19.6
⎯
ns
⎯
t_cyc
⎯
ns
⎯
t_cyc
200 ns
⎯
ns
Figure 19.7
⎯
ns
⎯
ns
⎯
ns
⎯
ns
100
ns
Figure 19.8
Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. The RES, MRES, NMI and IRQ3 to IRQ0 signals are asynchronous inputs, but when
the setup times shown here are observed, the signals are considered to have been
changed at clock rise (RES, MRES) or fall (NMI and IRQ3 to IRQ0). If the setup times
are not observed, detection of these signals may be delayed until the next clock rise or
fall.
Rev.2.00 Sep. 27, 2007 Page 428 of 448
REJ09B0394-0200