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SH7101 Datasheet, PDF (73/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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2. CPU
System Control Instructions
Table 2.17 System Control Instructions
Instruction
CLRT
CLRMAC
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
RTE
Instruction Code
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000000101011
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@âRn
STC.L GBR,@âRn
STC.L VBR,@âRn
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
Operation
Execu-
tion
States T Bit
0âT
1
0
0 â MACH, MACL
1
â¯
Rm â SR
1
LSB
Rm â GBR
1
â¯
Rm â VBR
1
â¯
(Rm) â SR, Rm + 4 â Rm 3
LSB
(Rm) â GBR, Rm + 4 â Rm 3
â¯
(Rm) â VBR, Rm + 4 â Rm 3
â¯
Rm â MACH
1
â¯
Rm â MACL
1
â¯
Rm â PR
1
â¯
(Rm) â MACH, Rm + 4 â Rm 1
â¯
(Rm) â MACL, Rm + 4 â Rm 1
â¯
(Rm) â PR, Rm + 4 â Rm 1
â¯
No operation
1
â¯
Delayed branch, stack area 4
â¯
â PC/SR
1âT
1
1
Sleep
3*
â¯
SR â Rn
1
â¯
GBR â Rn
1
â¯
VBR â Rn
1
â¯
Rn â 4 â Rn, SR â (Rn)
2
â¯
Rn â 4 â Rn, GBR â (Rn) 2
â¯
Rn â 4 â Rn, VBR â (Rn)
2
â¯
Rev.2.00 Sep. 27, 2007 Page 39 of 448
REJ09B0394-0200
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