SH7101 Datasheet, PDF (16/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8.3.14 Timer Dead Time Data Register (TDDR)............................................................. 135
8.3.15 Timer Period Data Register (TCDR) .................................................................... 135
8.3.16 Timer Period Buffer Register (TCBR).................................................................. 135
8.3.17 Bus Master Interface ............................................................................................. 136
8.4 Operation ........................................................................................................................... 137
8.4.1 Basic Functions..................................................................................................... 137
8.4.2 Synchronous Operation......................................................................................... 142
8.4.3 Buffer Operation ................................................................................................... 145
8.4.4 Cascaded Operation .............................................................................................. 149
8.4.5 PWM Modes ......................................................................................................... 150
8.4.6 Phase Counting Mode........................................................................................... 156
8.4.7 Reset-Synchronized PWM Mode.......................................................................... 163
8.4.8 Complementary PWM Mode................................................................................ 167
8.5 Interrupt Sources................................................................................................................ 192
8.5.1 Interrupts and Priorities......................................................................................... 192
8.5.2 A/D Converter Activation..................................................................................... 194
8.6 Operation Timing............................................................................................................... 195
8.6.1 Input/Output Timing ............................................................................................. 195
8.6.2 Interrupt Signal Timing......................................................................................... 200
8.7 Usage Notes ....................................................................................................................... 204
8.7.1 Module Standby Mode Setting ............................................................................. 204
8.7.2 Input Clock Restrictions ....................................................................................... 204
8.7.3 Caution on Period Setting ..................................................................................... 205
8.7.4 Contention between TCNT Write and Clear Operations...................................... 205
8.7.5 Contention between TCNT Write and Increment Operations............................... 206
8.7.6 Contention between TGR Write and Compare Match .......................................... 207
8.7.7 Contention between Buffer Register Write and Compare Match ......................... 208
8.7.8 Contention between TGR Read and Input Capture............................................... 210
8.7.9 Contention between TGR Write and Input Capture.............................................. 211
8.7.10 Contention between Buffer Register Write and Input Capture ............................. 212
8.7.11 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 212
8.7.12 Counter Value during Complementary PWM Mode Stop .................................... 214
8.7.13 Buffer Operation Setting in Complementary PWM Mode ................................... 214
8.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 215
8.7.15 Overflow Flags in Reset Sync PWM Mode.......................................................... 216
8.7.16 Contention between Overflow/Underflow and Counter Clearing......................... 217
8.7.17 Contention between TCNT Write and Overflow/Underflow................................ 218
8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronous PWM Mode........................................................................... 218
Rev.2.00 Sep. 27, 2007 Page xvi of xxxiv
REJ09B0394-0200