SH7101 Datasheet, PDF (429/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Power-Down Modes
17.3 Operation
17.3.1 Sleep Mode
Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0,
the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the
CPU's internal registers are retained. Peripheral functions except the CPU do not stop.
Clearing Sleep Mode: Sleep mode is cleared by the conditions below.
• Clearing by the power on reset
When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven
high after the elapse of the specified reset input period, the CPU starts the reset exception
handling. Also, when the internal power on reset is occurred, sleep mode is cleared.
• Clearing by the manual reset
When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual
reset state and thus sleep mode is cleared. Also, when the internal manual reset is occurred,
sleep mode is cleared.
Notes on Using Sleep Mode
• There are 4 conditions to clear sleep mode.
(1) Clearing by an interrupt
(2) Clearing by DTC address error
(3) Clearing by the power-on reset
(4) Clearing by the manual reset
When clearing sleep mode by (1) or (2), CPU may run out of control. Please clear sleep mode
by (3) or (4), don't use (1) or (2).
• Do not use DTC module or AUD module during sleep mode.
Rev.2.00 Sep. 27, 2007 Page 395 of 448
REJ09B0394-0200