SH7101 Datasheet, PDF (301/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Watchdog Timer
Bit Bit Name Initial Value R/W Description
2
CKS2
0
1
CKS1
0
0
CKS0
0
R/W Clock Select 2 to 0
R/W Select one of eight internal clock sources for input to
R/W
TCNT. The clock signals are obtained by dividing the
frequency of the system clock (φ). The overflow
frequency for φ = 40 MHz is enclosed in
parentheses*³.
000: Clock φ/2 (frequency: 12.8 μs)
001: Clock φ/64 (frequency: 409.6 μs)
010: Clock φ/128 (frequency: 0.8 ms)
011: Clock φ/256 (frequency: 1.6 ms)
100: Clock φ/512 (frequency: 3.3 ms)
101: Clock φ/1024 (frequency: 6.6 ms)
110: Clock φ/4096 (frequency: 26.2 ms)
111: Clock φ/8192 (frequency: 52.4 ms)
Notes: 1. Only a 0 can be written after reading 1.
2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what
happens when TCNT overflows in watchdog timer mode.
3. The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev.2.00 Sep. 27, 2007 Page 267 of 448
REJ09B0394-0200