SH7101 Datasheet, PDF (424/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Power-Down Modes
17.2 Register Descriptions
Registers related to power down modes are shown below. For details on register addresses and
register states during each process, refer to section 18, List of Registers.
• Standby control register (SBYCR)
• System control register (SYSCR)
• Module standby control register 1 (MSTCR1)
• Module standby control register 2 (MSTCR2)
17.2.1 Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Initial
Bit Bit Name Value R/W Description
7
SSBY
0
R/W Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction has
been executed
1: Shifts to software standby mode after the SLEEP
instruction has been executed
This bit cannot be set to 1 when the watchdog timer (WDT)
is operating (when the TME bit in TCSR of the WDT is set
to 1). When transferring to software standby mode, clear
the TME bit to 0, stop the WDT, then set the SSBY bit to 1.
6
HIZ
0
R/W Port High-Impedance
In software standby mode, this bit selects whether the pin
state of the I/O port is retained or changed to high-
impedance.
0: In software standby mode, the pin state is retained.
1: In software standby mode, the pin state is changed to
high-impedance.
The HIZ bit cannot be set to 1 when the TME bit in TCSR of
the WDT is set to 1.
When changing the pin state of the I/O port to high-
impedance, clear the TME bit to 0, then set the HIZ bit to 1.
Rev.2.00 Sep. 27, 2007 Page 390 of 448
REJ09B0394-0200